Thin-film-transistor (TFT) technology is important for fabrication of circuitry that requires the ability to flex and in large area devices such as flat panel displays, imagers, and detectors that require active areas that are large compared to the current size of semiconductor wafers. However, a significant limitation of the TFT technology results from the difficulty in fabricating useful PMOS devices in a-Si Amorphous silicon (a-Si) or other thin film semiconductor materials such as Zinc Oxide and thin-film polysilicon. As a result of this difficulty, many TFT circuits only use NMOS transistors, which can cause problems when trying to implement logic with full rail-to-rail output voltage levels, i.e., signals ranging from ground to the power supply voltage. In particular, TFT logic circuits generally lose signal level from the dynamic voltage range and therefore cannot be easily cascaded in the way that conventional CMOS circuits can.
FIG. 1 shows a circuit diagram for a conventional NMOS inverter 100 that can be fabricated using thin-film transistors in a-Si or other material. Inverter 100 includes two NMOS transistors 110 and 120. Transistor 110 has a gate and a drain connected to supply voltage Vdd and a source connected to an output node 115. Transistor 120 has a drain connected to output node 115, a gate connected to receive an input signal IN, and a source connected to ground.
In operation, when an input signal IN is high, ideally at supply voltage Vdd, transistor 120 carries a saturation current which also flows from supply voltage Vdd through transistor 110. Accordingly, when input signal IN is high, inverter 100 acts as a voltage divider, and output signal OUT is pulled to a voltage that will not be the ground voltage but instead depends on the sizes of transistors 110 and 120. When input signal IN is low (ideally at the ground voltage), transistor 120 will be off, and transistor 110 will pull up output node 115 to a voltage that is lower than supply voltage Vdd by at least the threshold voltage of transistor 110. Accordingly, the output signal OUT from inverter 100 does not have the full rail-to-rail voltage range from ground to supply voltage Vdd.
The problem of being unable to provide output signals with the full rail-to-rail voltage swings limits the number of such logic gates that may be serially connected or cascaded without additional signal correction or conditioning. Accordingly, systems and methods that are able to provide rail-to-rail signal range in TFT circuits and NMOS circuits are desired.